nvd-json-data-feeds/CVE-2024/CVE-2024-423xx/CVE-2024-42302.json

{
  "id": "CVE-2024-42302",
  "sourceIdentifier": "416baaa9-dc9f-4396-8d5f-8c081fb06d67",
  "published": "2024-08-17T09:15:10.487",
  "lastModified": "2024-08-22T16:37:26.237",
  "vulnStatus": "Analyzed",
  "cveTags": [],
  "descriptions": [
    {
      "lang": "en",
      "value": "In the Linux kernel, the following vulnerability has been resolved:\n\nPCI/DPC: Fix use-after-free on concurrent DPC and hot-removal\n\nKeith reports a use-after-free when a DPC event occurs concurrently to\nhot-removal of the same portion of the hierarchy:\n\nThe dpc_handler() awaits readiness of the secondary bus below the\nDownstream Port where the DPC event occurred.  To do so, it polls the\nconfig space of the first child device on the secondary bus.  If that\nchild device is concurrently removed, accesses to its struct pci_dev\ncause the kernel to oops.\n\nThat's because pci_bridge_wait_for_secondary_bus() neglects to hold a\nreference on the child device.  Before v6.3, the function was only\ncalled on resume from system sleep or on runtime resume.  Holding a\nreference wasn't necessary back then because the pciehp IRQ thread\ncould never run concurrently.  (On resume from system sleep, IRQs are\nnot enabled until after the resume_noirq phase.  And runtime resume is\nalways awaited before a PCI device is removed.)\n\nHowever starting with v6.3, pci_bridge_wait_for_secondary_bus() is also\ncalled on a DPC event.  Commit 53b54ad074de (\"PCI/DPC: Await readiness\nof secondary bus after reset\"), which introduced that, failed to\nappreciate that pci_bridge_wait_for_secondary_bus() now needs to hold a\nreference on the child device because dpc_handler() and pciehp may\nindeed run concurrently.  The commit was backported to v5.10+ stable\nkernels, so that's the oldest one affected.\n\nAdd the missing reference acquisition.\n\nAbridged stack trace:\n\n  BUG: unable to handle page fault for address: 00000000091400c0\n  CPU: 15 PID: 2464 Comm: irq/53-pcie-dpc 6.9.0\n  RIP: pci_bus_read_config_dword+0x17/0x50\n  pci_dev_wait()\n  pci_bridge_wait_for_secondary_bus()\n  dpc_reset_link()\n  pcie_do_recovery()\n  dpc_handler()"
    },
    {
      "lang": "es",
      "value": "En el kernel de Linux, se ha resuelto la siguiente vulnerabilidad: PCI/DPC: corrige el use-after-free en DPC simult\u00e1neos y la eliminaci\u00f3n en caliente. Keith informa un use-after-free cuando ocurre un evento de DPC simult\u00e1neamente con la eliminaci\u00f3n en caliente del mismo. parte de la jerarqu\u00eda: dpc_handler() espera que el bus secundario est\u00e9 listo debajo del puerto descendente donde ocurri\u00f3 el evento DPC. Para hacerlo, sondea el espacio de configuraci\u00f3n del primer dispositivo secundario en el bus secundario. Si ese dispositivo secundario se elimina simult\u00e1neamente, los accesos a su estructura pci_dev hacen que el kernel falle. Esto se debe a que pci_bridge_wait_for_secondary_bus() no mantiene una referencia en el dispositivo secundario. Antes de v6.3, la funci\u00f3n solo se llamaba al reanudar desde la suspensi\u00f3n del sistema o al reanudar el tiempo de ejecuci\u00f3n. Mantener una referencia no era necesario en aquel entonces porque el subproceso pciehp IRQ nunca pod\u00eda ejecutarse al mismo tiempo. (Al reanudar desde la suspensi\u00f3n del sistema, las IRQ no se habilitan hasta despu\u00e9s de la fase resume_noirq. Y la reanudaci\u00f3n del tiempo de ejecuci\u00f3n siempre se espera antes de que se elimine un dispositivo PCI). Sin embargo, a partir de v6.3, pci_bridge_wait_for_secondary_bus() tambi\u00e9n se llama en un evento DPC. El commit 53b54ad074de (\"PCI/DPC: Esperar la preparaci\u00f3n del bus secundario despu\u00e9s del reinicio\"), que introdujo eso, no pudo apreciar que pci_bridge_wait_for_secundary_bus() ahora necesita mantener una referencia en el dispositivo secundario porque dpc_handler() y pciehp pueden ejecutarse simult\u00e1neamente. El commit fue respaldada a n\u00facleos estables v5.10+, por lo que ese es el m\u00e1s antiguo afectado. Agregue la adquisici\u00f3n de referencia que falta. Seguimiento de pila abreviado: ERROR: no se puede manejar el error de p\u00e1gina para la direcci\u00f3n: 00000000091400c0 CPU: 15 PID: 2464 Comm: irq/53-pcie-dpc 6.9.0 RIP: pci_bus_read_config_dword+0x17/0x50 pci_dev_wait() pci_bridge_wait_for_secondary_bus() dpc_reset_link() _hacer_recuperaci\u00f3n () dpc_handler()"
    }
  ],
  "metrics": {
    "cvssMetricV31": [
      {
        "source": "nvd@nist.gov",
        "type": "Primary",
        "cvssData": {
          "version": "3.1",
          "vectorString": "CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:H",
          "attackVector": "LOCAL",
          "attackComplexity": "LOW",
          "privilegesRequired": "LOW",
          "userInteraction": "NONE",
          "scope": "UNCHANGED",
          "confidentialityImpact": "HIGH",
          "integrityImpact": "HIGH",
          "availabilityImpact": "HIGH",
          "baseScore": 7.8,
          "baseSeverity": "HIGH"
        },
        "exploitabilityScore": 1.8,
        "impactScore": 5.9
      }
    ]
  },
  "weaknesses": [
    {
      "source": "nvd@nist.gov",
      "type": "Primary",
      "description": [
        {
          "lang": "en",
          "value": "CWE-416"
        }
      ]
    }
  ],
  "configurations": [
    {
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          "operator": "OR",
          "negate": false,
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